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Altera_Forum's avatar
Altera_Forum
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8 years ago

Monitor wires inside module region ModelSim in gate -level or timing simulation

While doing gate-level simulation, i found an output miss-match in my design. I want to investigate it further but all the wire in module.vo files, that was previously assigned in module.v, was renam...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

All my pre-assign wire was renamed in module.vo. The renaming pattern is in the chaotic way that i cant understand. Checking each wire new name is quite trouble some, the module.vo is around 3,000,000 lines. Furthermore complex wires such as sim:/tb_Z/NNC/CalcEng/b_bus[179:160] is not easy to trace