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Altera_Forum
Honored Contributor
Honored ContributorMonitor wires inside module region ModelSim in gate -level or timing simulation
While doing gate-level simulation, i found an output miss-match in my design. I want to investigate it further but all the wire in module.vo files, that was previously assigned in module.v, was renam...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Yes, that's the panel I was referring to. --- Quote End --- Then, how do I get the appropriate wire? Renaming is the main problem.
