Monitor wires inside module region ModelSim in gate -level or timing simulation

In a simulation, you don't have to bring out wires to top-level ports to monitor them. I forget the panel names in ModelSim, but once you've compiled the files in ModelSim, you can select a part of the design hierarchy in the sim Library and then in the object (?) window, you should see a list of all the signals in that part of the design. Just click and drag them over to the waveform window and then start the simulation.