Monitor wires inside module region ModelSim in gate -level or timing simulation

https://alteraforum.com/forum/attachment.php?attachmentid=14874&stc=1 i have post an image screen shot on https://ibb.co/dmxcax . Those images show the difference of wires inside the NNC module in different simulation setup, functional and timing, of the same testbench. The right hand side is functional simulation objects invoking module.v, the left hand side is timing simulation objects invoking module.vo. Those twos have totally different wires, or at least totally different name. For more information, those simulation generated by Quartus Prime nativelink. In case I had done wrong procedure, the process was simply full compilation (Ctrl-L) then click Tools>Run Simulation Tool>RTL Simulation or Tools>Run Simulation Tool>Gate Level Simulation. I follow this instruction https://www.altera.com/en_us/pdfs/literature/ug/ug_gs_msa_qii.pdf for EDA Tool Settings.