merging VHDL and Verilog code

If you are refering to a merge in the same file then this cannot be done. You would need to rewrite the Verilog functions into VHDL or the other way around!

Quartus allows multiple languages so you should be able to use mixed Verilog and VHDL source files within your Quartus project

You can instance from VHDL a Verilog module and viceversa, each one in different files. This example shows how do it:

This is a VHDL entity called "White"

ENTITY white IS

PORT(

----------------------Inputs-------------------------------

clk : IN STD_LOGIC;

i_fval : IN STD_LOGIC;

i_media : IN STD_LOGIC_VECTOR(9 DOWNTO 0);

-------------------------------------------------------------

----------------------Outputs--------------------------------

o_enable : OUT STD_LOGIC;

o_exposure : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)

-------------------------------------------------------------

);

END white;

This is a Verilog code that instances a white module called white0

white white0(

.clk(CCD_PIXCLK),

.i_fval(MEDIA_sfval[9:0]),

.i_media(MEDIA_sa[9:0]),

.o_enable(senable),

.o_exposure(sbalance)

);

Quartus-II allows for a fluent intermixing of VHDL, Verilog, and schematics on the level of "modules" in Verilog, "entity/architectures" in Verilog and Blocks in schematics.

The naming and instantiation of the module in Verilog, entity/architecture in VHDL and blocks in schematics should be the same when using design entities among these different entry methods.

Besides that also the names of input/outputs/ios (Verilog) and ports (VHDL) or pins in schematics should correspond.

Hereby you should take notice that Verilog is case sensitive, while VHDL is not. So be careful to be consistent in naming.

Hope this helps...

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Hereby you should take notice that Verilog is case sensitive, while VHDL is not. So be careful to be consistent in naming.

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this is good advice to follow all the time. its painful to bring a project from Windows to Linux and deal with case sensitivity issues. :mad:

Hi everybody,

Thanks for all your replies.

As I see "the example from parrado" gives, is a way of writing the same code in vhdl and verilog.

I still don´t understand how I have to merge verilog and vhdl in a project?

Could anyone give me a short example of how to merge in a project?

sentronic,

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I still don´t understand how I have to merge verilog and vhdl in a project?

Could anyone give me a short example of how to merge in a project?

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assume you have design files in Verilog ( *.v ) and in VHDL ( *.vhd ). Simply add to your project in Quartus II.

Use the menu: "project" and submenu "add/remove files in project..." to add the *.v and .vhd files to your project.

When you create the files from scratch you can use: "file" and "new..." and select the appropriate file type Verilog or VHDL in the dialog window.

Hope this helps

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Quartus web edition or modelsim web edition (I don't remember) is restricted to use only ONE language.

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Quartus II Web Edition does support mixed languages.

ModelSim-Altera Edition does NOT support mixed languages.

:cool: