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Altera_Forum
Honored Contributor
Honored Contributormerging VHDL and Verilog code
Can anyone help whith how to merge VHDL code and Verilog code together? in somehow i have to combine VHDL and Verilog code??
Altera_ForumHonored Contributor
Honored ContributorIf you are refering to a merge in the same file then this cannot be done. You would need to rewrite the Verilog functions into VHDL or the other way around!
Quartus allows multiple languages so you should be able to use mixed Verilog and VHDL source files within your Quartus project
