merging VHDL and Verilog code

sentronic,

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I still don´t understand how I have to merge verilog and vhdl in a project?

Could anyone give me a short example of how to merge in a project?

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assume you have design files in Verilog ( *.v ) and in VHDL ( *.vhd ). Simply add to your project in Quartus II.

Use the menu: "project" and submenu "add/remove files in project..." to add the *.v and .vhd files to your project.

When you create the files from scratch you can use: "file" and "new..." and select the appropriate file type Verilog or VHDL in the dialog window.

Hope this helps