Altera_Forum
Honored Contributor
Honored Contributormerging VHDL and Verilog code
Can anyone help whith how to merge VHDL code and Verilog code together? in somehow i have to combine VHDL and Verilog code??
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Altera_ForumHonored Contributor
Honored ContributorQuartus Web edition is not restricted regarding mixed language programming. Otherwise many Altera Megafunctions wouldn't compile.
