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Altera_Forum
Honored Contributor
Honored Contributormerging VHDL and Verilog code
Can anyone help whith how to merge VHDL code and Verilog code together? in somehow i have to combine VHDL and Verilog code??
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hereby you should take notice that Verilog is case sensitive, while VHDL is not. So be careful to be consistent in naming. --- Quote End --- this is good advice to follow all the time. its painful to bring a project from Windows to Linux and deal with case sensitivity issues. :mad:
