Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributormerging VHDL and Verilog code
Can anyone help whith how to merge VHDL code and Verilog code together? in somehow i have to combine VHDL and Verilog code??
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Quartus web edition or modelsim web edition (I don't remember) is restricted to use only ONE language. --- Quote End --- Quartus II Web Edition does support mixed languages. ModelSim-Altera Edition does NOT support mixed languages. :cool:
