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Altera_Forum
Honored Contributor
Honored Contributormerging VHDL and Verilog code
Can anyone help whith how to merge VHDL code and Verilog code together? in somehow i have to combine VHDL and Verilog code??
Altera_ForumHonored Contributor
Honored ContributorHi everybody,
Thanks for all your replies. As I see "the example from parrado" gives, is a way of writing the same code in vhdl and verilog. I still don´t understand how I have to merge verilog and vhdl in a project? Could anyone give me a short example of how to merge in a project?
