Altera_Forum
Honored Contributor
Honored Contributormerging VHDL and Verilog code
Can anyone help whith how to merge VHDL code and Verilog code together? in somehow i have to combine VHDL and Verilog code??
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Altera_ForumHonored Contributor
Honored ContributorQuartus-II allows for a fluent intermixing of VHDL, Verilog, and schematics on the level of "modules" in Verilog, "entity/architectures" in Verilog and Blocks in schematics.
The naming and instantiation of the module in Verilog, entity/architecture in VHDL and blocks in schematics should be the same when using design entities among these different entry methods. Besides that also the names of input/outputs/ios (Verilog) and ports (VHDL) or pins in schematics should correspond. Hereby you should take notice that Verilog is case sensitive, while VHDL is not. So be careful to be consistent in naming. Hope this helps...
