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Nakaj's avatar
Nakaj
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1 year ago
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MAX V Exposed pad solder reflow problem

A reflow soldering failure occurred on the exposed pad on the bottom of the QFP64
pin device of the MAX V device. Please let me know if there is a recommended 
pattern layout for Exposed Pad.
Please let me know if there is a recommended value for the number and diameter of 
through holes to connect the exposed pad to the GND pattern.

Board Debug
  • FakhrulA_altera's avatar
    FakhrulA_altera
    1 year ago

    Thanks for your response, I now transition this thread to community support. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


16 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    stencil thickness is usually chosen by the assembly service provider depending on PCA technology and used pad range. As mentioned above, problem with EQFP package is the 0.05 to 0.15 mm range of exposed pad clearance. If the parts have typical 0.1 mm clearance, 120 µm standard stencil thickness should work, but for maximal 0.15 clearance you'll probably want a thicker stencil, e.g. 180 µm if it's still compatible with small pads used on the board.

    I'm presuming that you have industry standard reflow profile as suggested in AN353, because another possible reason for solder failure is "cold solder joint".

    Regards
    Frank

    • Nakaj's avatar
      Nakaj
      Icon for New Contributor rankNew Contributor
      1 year ago

      Thank you for your reply.

      your answer is very helpful.

      Regards

      Nakaj

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hi Nakaj,


    Apologies for the delay due to the end-year and New Year holidays. As mentioned in the AN353, you may refer to the latest IPC-A-610D Standard.


    Regards,

    Fakhrul


    • Nakaj's avatar
      Nakaj
      Icon for New Contributor rankNew Contributor
      1 year ago

      Thank you so much for your reply.

      But my question is still not resolved.

      Please tell me the temperature and heating time of the heater when removing the IC. How can I evaluate the effect on the circuit components on the back side of the IC to be removed?

      Regards

      Nakaj

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Thanks for your response, I now transition this thread to community support. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    what kind of failure do you observe, missing connection or short to other pins?

    I see a previous discussion related to 64-pin EQFP package https://community.intel.com/t5/Programmable-Devices/Max-V-Stencil-Design-64-Pin-Plastic-Enhanced-Quad-Flat-EQFP/m-p/1574520#M94757

    I think, a comfortable option is to place vias beneath the exposed pad, this way you don't need to care for solder drain through vias. As mentioned in my previous post, EQFP package has the problem of clearance tolerance between pad and PCB, about 0.05 to 0.15 mm. You need to supply suffient solder paste to safely bridge the gap.

    Regards
    Frank

    • Nakaj's avatar
      Nakaj
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      1 year ago

      Thank you for your reply.

      We have an issue with exposed pad not being connected. There may not be enough solder.

      Is there reccomended pattern layout for PCB?

      Regards

      Nakaj

    • Nakaj's avatar
      Nakaj
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      1 year ago

      Please also tell me the recommended thickness of the solder mask.

      Regards,

      Nakaj

    • Nakaj's avatar
      Nakaj
      Icon for New Contributor rankNew Contributor
      1 year ago

      Thank you for your reply.

      But I would like to know about reccomended pattern layout for PCB and recommended thickness of the solder mask of MAX V QFP64 device.

      Regards

      Nakaj

  • Nakaj's avatar
    Nakaj
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    1 year ago

    Thank you for your reply.

    If you find a solution please let me know.

    Regards

    Nakaj

    • Nakaj's avatar
      Nakaj
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      1 year ago

      Thank you for your reply.

      I would like to know about recommended thickness of the solder mask(stencil?) of MAX V QFP64 device.

      About reccomended pattern layout for PCB, I found a Cadence and mentor graphics CAD data in Intel website.

      PCB design engineer tries to analyse it.

      Regards

      Nakaj

  • Nakaj's avatar
    Nakaj
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi,

    Please let me know manufacturer's recommended conditions for MAX V rework(IC mounting by hand soldering).

    For example,heating temperature, heating time, tools etc.

    Is there a risk of overheating the IC during rework? (Deterioration, impact on lifespan, etc.)

    Regards

    Nakaj

  • Nakaj's avatar
    Nakaj
    Icon for New Contributor rankNew Contributor
    1 year ago

    Thank you for your reply.

    We decided not to do the rework due to customer request.
    This concludes my questions.

    Regards

    Nakaj