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Nakaj's avatar
Nakaj
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1 year ago
Solved

MAX V Exposed pad solder reflow problem

A reflow soldering failure occurred on the exposed pad on the bottom of the QFP64 pin device of the MAX V device. Please let me know if there is a recommended pattern layout for Exposed Pad. Plea...
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  • FakhrulA_altera's avatar
    FakhrulA_altera
    1 year ago

    Thanks for your response, I now transition this thread to community support. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,
what kind of failure do you observe, missing connection or short to other pins?

I see a previous discussion related to 64-pin EQFP package https://community.intel.com/t5/Programmable-Devices/Max-V-Stencil-Design-64-Pin-Plastic-Enhanced-Quad-Flat-EQFP/m-p/1574520#M94757

I think, a comfortable option is to place vias beneath the exposed pad, this way you don't need to care for solder drain through vias. As mentioned in my previous post, EQFP package has the problem of clearance tolerance between pad and PCB, about 0.05 to 0.15 mm. You need to supply suffient solder paste to safely bridge the gap.

Regards
Frank

  • Nakaj's avatar
    Nakaj
    Icon for New Contributor rankNew Contributor
    1 year ago

    Thank you for your reply.

    We have an issue with exposed pad not being connected. There may not be enough solder.

    Is there reccomended pattern layout for PCB?

    Regards

    Nakaj

  • Nakaj's avatar
    Nakaj
    Icon for New Contributor rankNew Contributor
    1 year ago

    Please also tell me the recommended thickness of the solder mask.

    Regards,

    Nakaj