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Altera_Forum's avatar
Altera_Forum
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11 years ago

LVDS issue - Black magic anyone?

I have an LVDS related issue that drives me crazy:

There are two boards with a FPGA that are connected by a ca. 30cm cable. Only 6 wires are used:

GND + Power

LVDS (with embedded clock), 720Mbps

UART (Rxd + Txd)

(The cable is unshielded for flexibility reasons)

The cable is a "flat Ethernet cable" with 4 twisted pairs, one pair is unused, one pair is LVDS, one pair is GND + Rxd and the last is Power + TxD.

Most cables work fine with a low error rate. However, some cables of the same batch have an excessive error rate. These cables have no visible difference to the good cables.

The ends of the cable have the outer isolation removed for about 5cm, the LVDS pair is twisted also for this 5cm, the other wires are straight crimped to the connector.

Now the strange behavior: When touching the cable at some positions by hand, the bad cables are suddenly perfect or at least much better. And the even stranger thing: When touching at the last 5cm, it is NOT the touching of the LVDS pair that makes the difference, but the touching the GND/Power/Uart wires! This can be observed on both sides of the cable.

It is really only "the hand" that makes the difference, strapping together the wires does not help. It does also not look like a mechanical problem of the cable.

I tried changing and even removing the termination resistors, this did not change the behavior at all. I have changed both boards, it is really the cable that makes the difference.

Has anybody an idea what the reason of this behavior could be?

Regards,

Thomas

www.entner-electronics.com (http://www.entner-electronics.com) - Home of EEBlaster

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Hi Thomas,

    Do you have a scope that can view all the signals at once, or at least see that signals that have bit-errors, to see how those signals change when you touch the cable?

    What happens when you slow things down? (If that is possible in this design)

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    Hi Dave,

    unfortunately I only have a 500MHz scope. With that I cannot measure a meaningful eye diagram, etc. . I have looked at all the signals nevertheless, but I cannot see any change of the signals when touching the cables. Only the dramatic effect on the error rate...

    What surprises me that applying the probes (capactive load) does show almost no effect while touching the cables does.

    It is not easily possible to slow the link down.

    Regards,

    Thomas
  • Altera_Forum's avatar
    Altera_Forum
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    A short LVDS link should perform better.

    Touching an unshielded pair will particularly attenuate common mode signals. To get problems as described, there must be a problem like:

    - link operated near maximum LVDS speed supported by the device family

    - bad termination

    - crosstalk of other signals

    - unsuitable clock recovery method or wrongly adjusted sampling window

    Can you tell something about the device family and IP for embedded clock recovery?
  • Altera_Forum's avatar
    Altera_Forum
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    It is a transceiver input of a Cyclone IV GX, operating in "basic" mode with a simple format (like DS92LV1023, not DC balanced). (We have multiple lanes, some using also regular LVDS inputs with our own IP for CDR, on these we do not see this behavior, only the transceiver inputs are making this problems.)

    I started to play around with the equalizer and DC gain setting, this appears to be the right screws to turn... Will provide more details later.
  • Altera_Forum's avatar
    Altera_Forum
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    Hmm, I guess this is solved now:

    We have used an equalizer setting of "Medium High" and gain 0. I guess this was the default value of the Wizard. It looks like for such a short cable, the equalizer is contra-productive.

    When I either increase the gain or reduce the equalizer setting to low, things get perfect with every cable. When I increase the equalizer setting to high, even with touching I still get transmission errors.

    Some questions are still open:

    - Are there any recommendations which gain settings should be used? (e.g. depending on Vdiff at the receiver?)

    - Can the actually used equalizer setting be seen anywhere in the compilation report?

    It turned out that the used cable is twisted with a low turn count (about one full turn every 20cm) -> I guess this causes some cross-talk to the other pairs which then get "touch sensitive". And because of the bad equalizer setting things were only marginally working and therefore the touching had such a strong effect. But some bad feeling is still left behind...

    Regards,

    Thomas

    www.entner-electronics.com - Home of EEBlaster
  • Altera_Forum's avatar
    Altera_Forum
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    Thomas,

    In your first post you said that the signal had an embedded clock, but then later, that you were using basic mode, and the signal was not DC balanced. What protocol are you using over the link? I assume the transceiver lane is DC connected to the receiver input. What logic standard does the transmitter use, eg., is it another Cyclone IV GX transmitter channel, or is it an LVDS transmitter? The Cyclone IV Handbook Table 1.2 on p291 (PDF page number) indicates that the DC coupled common-mode for LVDS is 0.82V, rather than the normal 1.2V or so. If you do control the logic at either-side of the link, you could consider using a DC balanced protocol and then AC coupling.

    Regarding the receiver settings. I use the eyeQ sweep feature on the Stratix IV and Arria V series devices. Unfortunately, the Cyclone IV devices do not have this feature. However, if you had a development kit with an Arria V device on it, you could use the feature to look at the performance of your cable. The typical way to "optimize" the transceiver settings is to use the Transceiver Toolkit, and run its sweep tests. The Transceiver Toolkit examples are here;

    http://www.altera.com/support/examples/on-chip-debugging/on-chip-debugging.html

    Unfortunately, there are no Cyclone IV GX examples. However, it would be simple enough to create a Qsys system with pattern-generator and checker, and then connect to a Cyclone IV GX transceiver in "basic" mode, and then perform a link test. That assumes however, that you can control both ends of the link.

    If that sounds like a test you want to do, we can chat about it some more. I have a couple of Cyclone IV GX Starter kits that I could link together (via their PCIe edge connectors) to see if the concept works.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    Hi Dave,

    you are right, it is DC connected. I think we have discussed this Vcm issue already in the past. The new board revision has this solved in a clean way. The revision we are talking about here has 1k3 pull-downs on both lanes to pull the Vcm into the correct region (quite ugly, but it works...).

    I think the settings I use now (min. equalizer, max. gain) work very well, I haven't seen any error anymore.

    The eyeQ feature looks interesting, unfortunately Arria (and Stratix) are too expensive for our typical projects. Maybe we will use Arria 10 somewhen in the future...

    Regards,

    Thomas
  • Altera_Forum's avatar
    Altera_Forum
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    Hi Thomas,

    --- Quote Start ---

    you are right, it is DC connected. I think we have discussed this Vcm issue already in the past. The new board revision has this solved in a clean way. The revision we are talking about here has 1k3 pull-downs on both lanes to pull the Vcm into the correct region (quite ugly, but it works...).

    --- Quote End ---

    Rather than using two pull-downs of the same value, it can be useful to use two slightly different values, so that the static voltage difference on the input results in a logic 0 or 1 when there is no input. You can use SignalTap II logic analyzer to see what the input does when not connected to your cable.

    --- Quote Start ---

    I think the settings I use now (min. equalizer, max. gain) work very well, I haven't seen any error anymore.

    --- Quote End ---

    Excellent.

    --- Quote Start ---

    The eyeQ feature looks interesting, unfortunately Arria (and Stratix) are too expensive for our typical projects. Maybe we will use Arria 10 somewhen in the future...

    --- Quote End ---

    Yeah, I understand that they are expensive, but if you consider them a piece of test equipment, then you only need one. Another alternative is a PHY device from Vitesse with their VScope feature (another eye pattern tool). If you are interested, take a look at the Arria V devices and see if you can find a low-cost kit with the transceivers exposed, or create a simple board with an Arria V device. The eyeQ feature on the Arria V GZ devices works nicely at over 10Gbps.

    Cheers,

    Dave