Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

LVDS issue - Black magic anyone?

I have an LVDS related issue that drives me crazy: There are two boards with a FPGA that are connected by a ca. 30cm cable. Only 6 wires are used: GND + Power LVDS (with embedded clock),...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

A short LVDS link should perform better.

Touching an unshielded pair will particularly attenuate common mode signals. To get problems as described, there must be a problem like:

- link operated near maximum LVDS speed supported by the device family

- bad termination

- crosstalk of other signals

- unsuitable clock recovery method or wrongly adjusted sampling window

Can you tell something about the device family and IP for embedded clock recovery?