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Altera_Forum
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11 years ago

LVDS issue - Black magic anyone?

I have an LVDS related issue that drives me crazy: There are two boards with a FPGA that are connected by a ca. 30cm cable. Only 6 wires are used: GND + Power LVDS (with embedded clock),...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi Dave,

unfortunately I only have a 500MHz scope. With that I cannot measure a meaningful eye diagram, etc. . I have looked at all the signals nevertheless, but I cannot see any change of the signals when touching the cables. Only the dramatic effect on the error rate...

What surprises me that applying the probes (capactive load) does show almost no effect while touching the cables does.

It is not easily possible to slow the link down.

Regards,

Thomas