LVDS issue - Black magic anyone?

Thomas,

In your first post you said that the signal had an embedded clock, but then later, that you were using basic mode, and the signal was not DC balanced. What protocol are you using over the link? I assume the transceiver lane is DC connected to the receiver input. What logic standard does the transmitter use, eg., is it another Cyclone IV GX transmitter channel, or is it an LVDS transmitter? The Cyclone IV Handbook Table 1.2 on p291 (PDF page number) indicates that the DC coupled common-mode for LVDS is 0.82V, rather than the normal 1.2V or so. If you do control the logic at either-side of the link, you could consider using a DC balanced protocol and then AC coupling.

Regarding the receiver settings. I use the eyeQ sweep feature on the Stratix IV and Arria V series devices. Unfortunately, the Cyclone IV devices do not have this feature. However, if you had a development kit with an Arria V device on it, you could use the feature to look at the performance of your cable. The typical way to "optimize" the transceiver settings is to use the Transceiver Toolkit, and run its sweep tests. The Transceiver Toolkit examples are here;

http://www.altera.com/support/examples/on-chip-debugging/on-chip-debugging.html

Unfortunately, there are no Cyclone IV GX examples. However, it would be simple enough to create a Qsys system with pattern-generator and checker, and then connect to a Cyclone IV GX transceiver in "basic" mode, and then perform a link test. That assumes however, that you can control both ends of the link.

If that sounds like a test you want to do, we can chat about it some more. I have a couple of Cyclone IV GX Starter kits that I could link together (via their PCIe edge connectors) to see if the concept works.

Cheers,

Dave