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Altera_Forum
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12 years ago

LVDS issue - Black magic anyone?

I have an LVDS related issue that drives me crazy: There are two boards with a FPGA that are connected by a ca. 30cm cable. Only 6 wires are used: GND + Power LVDS (with embedded clock),...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Hi Thomas,

Do you have a scope that can view all the signals at once, or at least see that signals that have bit-errors, to see how those signals change when you touch the cable?

What happens when you slow things down? (If that is possible in this design)

Cheers,

Dave