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Altera_Forum
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11 years ago

LVDS issue - Black magic anyone?

I have an LVDS related issue that drives me crazy: There are two boards with a FPGA that are connected by a ca. 30cm cable. Only 6 wires are used: GND + Power LVDS (with embedded clock),...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Hi Dave,

you are right, it is DC connected. I think we have discussed this Vcm issue already in the past. The new board revision has this solved in a clean way. The revision we are talking about here has 1k3 pull-downs on both lanes to pull the Vcm into the correct region (quite ugly, but it works...).

I think the settings I use now (min. equalizer, max. gain) work very well, I haven't seen any error anymore.

The eyeQ feature looks interesting, unfortunately Arria (and Stratix) are too expensive for our typical projects. Maybe we will use Arria 10 somewhen in the future...

Regards,

Thomas