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Altera_Forum
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11 years ago

LVDS issue - Black magic anyone?

I have an LVDS related issue that drives me crazy: There are two boards with a FPGA that are connected by a ca. 30cm cable. Only 6 wires are used: GND + Power LVDS (with embedded clock),...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

It is a transceiver input of a Cyclone IV GX, operating in "basic" mode with a simple format (like DS92LV1023, not DC balanced). (We have multiple lanes, some using also regular LVDS inputs with our own IP for CDR, on these we do not see this behavior, only the transceiver inputs are making this problems.)

I started to play around with the equalizer and DC gain setting, this appears to be the right screws to turn... Will provide more details later.