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Altera_Forum's avatar
Altera_Forum
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15 years ago

LOW Power VS. DUAL-EDGE TRIGGERED FLIP-FLOPS

Hi !guys,

the book Advanced FPGA Design by STEVE KILTS says DUAL-EDGE TRIGGERED FLIP-FLOPS can help reduce power.

this is his refernce code:

module dualedge(

output reg dataout,

input clk, datain);

reg ff0, ff1;

always @(posedge clk)

ff0 <= datain;

always @(posedge clk or negedge clk) begin

ff1 <= ff0;

dataout <= ff1;

end

endmodule

BUT,this code can not work,QUARTUS 80 give me this error:"Error (10239): Verilog HDL Always Construct error at dualedge.v(7): event control cannot test for both positive and negative edges of variable "clk""

Dose Altera's Device support this type of dff?

AND,Is STEVE KILTS's strategy to lower the power is useful?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    can anybody help me?

    I need to know whether it is wise to use dual-edge triggered flip-flops to save energe and whether it is advised in FPGA design.

    (The author STEVE KILTS says,bacause I=V*C*f and the dual-edge triggered flip-flops can half the required clk frequence,the power cost must be lesser than before.)
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You answered the question yourself. Dual edge clock FF aren't synthesizable in almost any FPGA of any vendor. So obviously, they can't save energy. If I remember right, they are are supported by a few CPLD architectures. I'm unable to determine, if the author's assumption is correct at all, because a dual-edge clock FF also needs more logic gates, so the promised benefit may be dwarted. But the question only arises for ASIC design, where you're free to tailor FFs according to your needs.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thank you.

    From google, I find out XILINX's CoolRunner ii Family CPLD support this kind of FF ,i don't know whether Altera have the similar products.

    And the author himself has sayed it is not always the best method for devices which don't support DUAL-EDGE TRIGGERED FLIP-FLOPS.

    A new question arise for me,why nowadays FPGA vender don't support this technique.Why this type of FF is not suitable for FPGA?

    Best wishes!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Sorry this came rather late. Anyway, just for those of you who wish to implement dual-edge FFs, here's a simple VHDL example (there are a few others - I know another implementation that works as well): 

        dualEdgeTriggered: process(reset,clk) is
        variable q1,q2:std_ulogic_vector(q'length-1 downto 0);
    begin
        if reset='1' then q1:=(others=>'0'); q2:=(others=>'0');
        elsif rising_edge(clk) then q1:=d xor q2;
        elsif falling_edge(clk) then q2:=d xor q1;
        end if;
        q<=q1 xor q2;
    end process;
    Not sure if this still works, but I've had success with this before.

    Regarding power consumption, yes you will generally have more gates, but doing this *could* save you from creating another higher speed clock that's double the rate, which will of course draw much more power.