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Honored Contributor

15 years ago

LOW Power VS. DUAL-EDGE TRIGGERED FLIP-FLOPS

Hi !guys, the book Advanced FPGA Design by STEVE KILTS says DUAL-EDGE TRIGGERED FLIP-FLOPS can help reduce power. this is his refernce code: module dualedge( output reg data...

Altera_Forum

Honored Contributor

14 years ago

Here's the 2-process implementation by Ralf: http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf

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LOW Power VS. DUAL-EDGE TRIGGERED FLIP-FLOPS

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