LOW Power VS. DUAL-EDGE TRIGGERED FLIP-FLOPS

You answered the question yourself. Dual edge clock FF aren't synthesizable in almost any FPGA of any vendor. So obviously, they can't save energy. If I remember right, they are are supported by a few CPLD architectures. I'm unable to determine, if the author's assumption is correct at all, because a dual-edge clock FF also needs more logic gates, so the promised benefit may be dwarted. But the question only arises for ASIC design, where you're free to tailor FFs according to your needs.