LOW Power VS. DUAL-EDGE TRIGGERED FLIP-FLOPS

Sorry this came rather late. Anyway, just for those of you who wish to implement dual-edge FFs, here's a simple VHDL example (there are a few others - I know another implementation that works as well):

    dualEdgeTriggered: process(reset,clk) is
        variable q1,q2:std_ulogic_vector(q'length-1 downto 0);
    begin
        if reset='1' then q1:=(others=>'0'); q2:=(others=>'0');
        elsif rising_edge(clk) then q1:=d xor q2;
        elsif falling_edge(clk) then q2:=d xor q1;
        end if;
        q<=q1 xor q2;
    end process;

Not sure if this still works, but I've had success with this before.

Regarding power consumption, yes you will generally have more gates, but doing this *could* save you from creating another higher speed clock that's double the rate, which will of course draw much more power.