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Altera_Forum
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15 years ago

LOW Power VS. DUAL-EDGE TRIGGERED FLIP-FLOPS

Hi !guys, the book Advanced FPGA Design by STEVE KILTS says DUAL-EDGE TRIGGERED FLIP-FLOPS can help reduce power. this is his refernce code: module dualedge( output reg data...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Thank you.

From google, I find out XILINX's CoolRunner ii Family CPLD support this kind of FF ,i don't know whether Altera have the similar products.

And the author himself has sayed it is not always the best method for devices which don't support DUAL-EDGE TRIGGERED FLIP-FLOPS.

A new question arise for me,why nowadays FPGA vender don't support this technique.Why this type of FF is not suitable for FPGA?

Best wishes!