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Altera_Forum
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16 years ago

LOW Power VS. DUAL-EDGE TRIGGERED FLIP-FLOPS

Hi !guys, the book Advanced FPGA Design by STEVE KILTS says DUAL-EDGE TRIGGERED FLIP-FLOPS can help reduce power. this is his refernce code: module dualedge( output reg data...
Altera_Forum's avatar
Altera_Forum
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16 years ago

can anybody help me?

I need to know whether it is wise to use dual-edge triggered flip-flops to save energe and whether it is advised in FPGA design.

(The author STEVE KILTS says,bacause I=V*C*f and the dual-edge triggered flip-flops can half the required clk frequence,the power cost must be lesser than before.)