Honored ContributorHi,all,
I want to ask is it costs a lot of resource or time delay to determine when using the sentence "if (vir+M)>500 then" ,here vir and M are both integer type. Thanks in advance.
Honored ContributorThe arithmetic complexity depends on the integer range, at worst case, vir and M can be both 32 bit signed numbers. (You shouldn't have integer signals without a range specification in synthesized VHDL anyway).
To find the exact resource consumption and delay with your FPGA family, compiling a test component/design is the easiest way. But it should fit a 50 - 100 MHz clock cycle in usual synchronous designs.Honored Contributoradders and comparators are pretty cheap. But as FvM says, make sure you constrain vir and M.
Personally, Id probably register vir + M before doing the compare, to keep the clock speed up.Honored ContributorHi，all.
Thanks for reply in detail.That's the answer to the question that I don't know which arithmetic is expensive.I also think we'd better register the result before doing the compare.Honored ContributorIf you don't need the DSP blocks on the device you can use these... this will save a lot of resources and allow a very high fmax..
Honored ContributorFPGA logic array blocks are usually handling the add/sub/compare operations. Cyclone family has no add function with it's embedded multipliers. Stratix has multiply/add combinations, but it would be rarely used for simple add operation, I think.
Honored ContributorHonored ContributorHonored ContributorDSP blocks (they are designated "embedded multipliers" with Cyclone family) only if needed. You can check in the physical netlist of your design.
Honored ContributorWhat's functional simulation in Altera-Modelsim? Is it EDA RTL simulation？
