Altera_ForumHonored Contributor16 years agolittle question about VHDL Hi,all, I want to ask is it costs a lot of resource or time delay to determine when using the sentence "if (vir+M)>500 then" ,here vir and M are both integer type. Thanks in advance.Show More
Altera_ForumHonored Contributor16 years agoWhat's functional simulation in Altera-Modelsim? Is it EDA RTL simulation?
Recent DiscussionsWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?System PLL of Agliex5 PCIE example design cannot be locked after configurationJTAG Chain Broken on Agilex 7-I Dev KitRequest for Cyclone V Pinout File InformationCyclone 10 LP's Extended Industrial parts