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Altera_Forum
Honored Contributor
Honored Contributorlittle question about VHDL
Hi,all, I want to ask is it costs a lot of resource or time delay to determine when using the sentence "if (vir+M)>500 then" ,here vir and M are both integer type. Thanks in advance.
Altera_ForumHonored Contributor
Honored ContributorThe arithmetic complexity depends on the integer range, at worst case, vir and M can be both 32 bit signed numbers. (You shouldn't have integer signals without a range specification in synthesized VHDL anyway).
To find the exact resource consumption and delay with your FPGA family, compiling a test component/design is the easiest way. But it should fit a 50 - 100 MHz clock cycle in usual synchronous designs.
