little question about VHDL

The arithmetic complexity depends on the integer range, at worst case, vir and M can be both 32 bit signed numbers. (You shouldn't have integer signals without a range specification in synthesized VHDL anyway).

To find the exact resource consumption and delay with your FPGA family, compiling a test component/design is the easiest way. But it should fit a 50 - 100 MHz clock cycle in usual synchronous designs.