Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

little question about VHDL

Hi,all, I want to ask is it costs a lot of resource or time delay to determine when using the sentence "if (vir+M)>500 then" ,here vir and M are both integer type. Thanks in advance.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

FPGA logic array blocks are usually handling the add/sub/compare operations. Cyclone family has no add function with it's embedded multipliers. Stratix has multiply/add combinations, but it would be rarely used for simple add operation, I think.