JTAG Test SW Issue (JTAG TopProbe)

Question

Hi,&nbsp;I used JTAG TopProbe als Boundary Scan SW to change / read level at FPGA pins in the past successfully with Cyclone II designs. Unfortunately I ran into issues with newer designs using Cyclone IV, Cyclone 10 or MAX10 devices. With these devices I cannot set any output levels, the SW just supports reading external applied high or low signals. I know the SW is quite old, does not "do" much more than setting and watching pins and is also no longer develope actively. Thus, I'd also be happy with any suggestion for newer ("cheap") SW to use for this simple connectivity checks I'd planned to do.&nbsp;(I meanwhile tried to use JTAGLive (JTAG Buzz, freeware), which failed to recognize the USB Blaster unfortunately.)Any other SW suggestions (or "secret unlocks" for JTAG TopProbe) are apprechiated :-)KR Carlhermann&nbsp;

fvm · Answer

Hi,I'm using latest TopJTAG Probe version 1.7.5 build 1551 with MAX10, Cyclone 10 LP and Cyclone 10 GX through USB Blaster and Arrow USB Programmer 2 (Generic FTDI 2232).&nbsp;Main application is initial test of new PCB designs or fault finding. No problems to set I/O pins with EXTEST instruction.Regards Frank

carlhermann · Answer

Hi,thank you for providing feedback.I'am using same version with the BSDL File downloaded from altera (intel) server. Thought the issue could be linked with this comment in the BSDL file, as on the QMTech Dev.Board W6 is pulled high (being acc. to PinOut File a standard IO, no special function pin)."-- You must run the Boundary Scan test in post-configuration mode if-- any of the following pins are connected to any termination resistor:-- U11, E14, W6, U12, G15, B7, E16."Curiously enough few Pins are changing (E4 is connected to a LED, thus I tried this one):to&nbsp;while others don't(E3 changes from 1/1 to 1/0 rather 1/1 to 0/0 as E4 with physical value constant High).Tried also with pull-up removed, no change in behaviour...&nbsp;&nbsp;&nbsp;

fvm · Answer

Hi,which Cyclone 10 FPGA and QMTech board is it?I also noticed comment in Cyclone 10 BSDL file, that it's only intended for testing unconfigure FPGA. With TopJTAG, I never worried about this point and had no problems to perform intended tests with Altera provided BSDL files. I already guessed that TopJTAG does the required translation, if any.I specifically don't understand why some pins seem to require special handling.See also Cyclone 10LP Post Configuration BSDL | Altera CommunityRegardsFrank&nbsp;

farabi · Answer

Hello,&nbsp;
&nbsp;
1. Please make sure you are using latest BSDL file.&nbsp;
2. Please make sure you JTAG/BST logic is enabled before running EXTEST.&nbsp;
3. Cyclone IV GX adds IEEE 1149.6 cells for AC-coupled transceivers, which differ from standard IO cells. Please make sure the tool you are using understand those particular cells. Otherwise, it only run samples. Regular IO is using IEEE 1149.1.&nbsp;
&nbsp;
regards,Farabi

carlhermann · Answer

Hi,&nbsp;the issue is related to the Dev.Board comes with a pre-programmed configuration.As the USB-Blaster JTAG I/F lacks the (optional) JTAG Reset-Line, the FPGA is already on power up in "post configuration" mode, even with the JTAG-Reset command by TopJTAG. Thus, only the pins used as outputs in this configuration can be set/reset by TopJTAG.&nbsp;I cleared the FLASH, thus the FPGA is now unconfigured at power up and by this all I/O pins are now controllable by TopJTAG :-)KRCarlhermann&nbsp;

Forum Discussion

JTAG Test SW Issue (JTAG TopProbe)

6 Replies

Recent Discussions

How to set initial register values after powerup

USB Blaster not available

Arria 10: Remote Update Watchdog unpredicted behavior

To INTEL - Request for Compliance Data from Analog Devices, Inc

VID setting is incorrect for Stratix 10. I am using MP2975GU as the voltage regulator.