Forum Discussion

Carlhermann's avatar
Carlhermann
Icon for Occasional Contributor rankOccasional Contributor
8 months ago

JTAG Test SW Issue (JTAG TopProbe)

Hi,  I used JTAG TopProbe als Boundary Scan SW to change / read level at FPGA pins in the past successfully with Cyclone II designs. Unfortunately I ran into issues with newer designs using Cyclone ...
Generic Io
Programmable Logic Device
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
8 months ago

Hi,
which Cyclone 10 FPGA and QMTech board is it?

I also noticed comment in Cyclone 10 BSDL file, that it's only intended for testing unconfigure FPGA. With TopJTAG, I never worried about this point and had no problems to perform intended tests with Altera provided BSDL files. I already guessed that TopJTAG does the required translation, if any.

I specifically don't understand why some pins seem to require special handling.

See also Cyclone 10LP Post Configuration BSDL | Altera Community

Regards
Frank

 

  • Farabi_Altera's avatar
    Farabi_Altera
    Icon for Regular Contributor rankRegular Contributor
    7 months ago

    Hello, 

     

    1. Please make sure you are using latest BSDL file. 

    2. Please make sure you JTAG/BST logic is enabled before running EXTEST. 

    3. Cyclone IV GX adds IEEE 1149.6 cells for AC-coupled transceivers, which differ from standard IO cells. Please make sure the tool you are using understand those particular cells. Otherwise, it only run samples. Regular IO is using IEEE 1149.1. 

     

    regards,
    Farabi