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Carlhermann's avatar
Carlhermann
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2 months ago

JTAG Test SW Issue (JTAG TopProbe)

Hi,  I used JTAG TopProbe als Boundary Scan SW to change / read level at FPGA pins in the past successfully with Cyclone II designs. Unfortunately I ran into issues with newer designs using Cyclone ...
Generic Io
Programmable Logic Device
Carlhermann's avatar
Carlhermann
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

Hi,
thank you for providing feedback.
I'am using same version with the BSDL File downloaded from altera (intel) server. Thought the issue could be linked with this comment in the BSDL file, as on the QMTech Dev.Board W6 is pulled high (being acc. to PinOut File a standard IO, no special function pin).
"
-- You must run the Boundary Scan test in post-configuration mode if
-- any of the following pins are connected to any termination resistor:
-- U11, E14, W6, U12, G15, B7, E16.
"
Curiously enough few Pins are changing (E4 is connected to a LED, thus I tried this one):

to 

while others don't




(E3 changes from 1/1 to 1/0 rather 1/1 to 0/0 as E4 with physical value constant High).

Tried also with pull-up removed, no change in behaviour...