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Carlhermann's avatar
Carlhermann
Icon for Occasional Contributor rankOccasional Contributor
8 months ago

JTAG Test SW Issue (JTAG TopProbe)

Hi,  I used JTAG TopProbe als Boundary Scan SW to change / read level at FPGA pins in the past successfully with Cyclone II designs. Unfortunately I ran into issues with newer designs using Cyclone ...
Generic Io
Programmable Logic Device
Carlhermann's avatar
Carlhermann
Icon for Occasional Contributor rankOccasional Contributor
7 months ago

Hi, 
the issue is related to the Dev.Board comes with a pre-programmed configuration.
As the USB-Blaster JTAG I/F lacks the (optional) JTAG Reset-Line, the FPGA is already on power up in "post configuration" mode, even with the JTAG-Reset command by TopJTAG. Thus, only the pins used as outputs in this configuration can be set/reset by TopJTAG. 
I cleared the FLASH, thus the FPGA is now unconfigured at power up and by this all I/O pins are now controllable by TopJTAG :-)
KR
Carlhermann 

  • Farabi_Altera's avatar
    Farabi_Altera
    Icon for Regular Contributor rankRegular Contributor
    7 months ago

    Hello, 

     

    Cool. Glad to hear your workaround works. 

     

    regards,
    Farabi