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Altera_Forum's avatar
Altera_Forum
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8 years ago

Is CPLD required for booting CYCLONE 5 FPGA from QSPI flash.

in cyclone 5- fpga can’t able to fetch the program from spi flash

FPGA - cyclone 5 (5cgtfd7d5f27i7n)

SPI FLASH - epcq128si16n

in our board only one spi flash (configuration flash) is there which is connected to dedicated pins of fpga,no cpld ,no other flash is there.

1. I have created LED program in quartux2, generated .sof file, and programmed it in to FPGA its working the LED’s are blinking and CONFIG_DONE LED also glowing.

2. I converted .sof to .jic, and programmed to SPI flash, it IS successfully programmed .It means that program is successfully written on SPI FLASH.

3. While I press reset button(making fpga_nconfig low), than LED not blinking, CONFIG DONE LED also not glowing it means that FPGA is not able to fetch the program from SPI FLASH.

same process i tried in two evaluation board as given below it is working -

I tried .JIC method on cyclone5 GT evaluation board and cyclone5 Gx .

In this board FPGA is booting from SPI flash after Power ON.

In both evaluation board CPLD is also in between FPGA and QSPI flash.

In our custum board CPLD is not used between FPGA and QSPI flash.

Is CPLD required for booting FPGA from flash or not ?

IN two board we have seen that .JIC is working ,in both board CPLD is there.

So my doubt is without CPLD it may be .jic process will not work , if some other process is there than you tell me that procedure through NIOS2 ,I will try that procedure in our board.

THANKS & REGARDS

Deepak kumar

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    No. You do not need a CPLD to boot the FPGA from FLASH.

    How are your MSEL pins set?

    Are you seeing a configuration clock to the FLASH device?

    Do you see nSTATUS going off during configuration - indicating an error?

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Suggest to review DevKit schematic and reference manual. The 5GT board has different configuration options that are controlled by MAX V CPLD and additional logic. It has also DIP switches to select different MSEL settings. A standard AS configuration scheme uses fixed connections and MSEL settings without needing additional logic.

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi,

    MSEL[3:0] pins are set to AS configuration 10011.(Even i tried 10010 also).

    During Flash programming we are able to see configuration clock(less than 10MHz).

    During configuration nstatus is not going low .

    after FLASH programming when we power cycle the board/RESET the board than nstatus is toggling .

    Thanks & Regards

    DEEPAK
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    During configuration nstatus is not going low

    --- Quote End ---

    Do you mean during FLASH programming nSTATUS is not going low?

    nSTATUS toggling when you reset/power cycle is not good, it suggests the FPGA is seeing an error. How quickly is it toggling and what are the other configuration signals (DCLK, nCONFIG, DATA0) doing relative to nSTATUS?

    If possible, I suggest you post some of your schematic.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    Do you mean during FLASH programming nSTATUS is not going low?

    nSTATUS toggling when you reset/power cycle is not good, it suggests the FPGA is seeing an error. How quickly is it toggling and what are the other configuration signals (DCLK, nCONFIG, DATA0) doing relative to nSTATUS?

    If possible, I suggest you post some of your schematic.

    Cheers,

    Alex

    --- Quote End ---

    I attached the flash and power module schematic.

    Nstatus is toggling that time duty cylce is 60(off time 40).

    I attached the scope shot after programming flash when i power cycle the board.

    Regards

    Deepak
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I can't see anything wrong with the schematic. You don't have any series resistors in any of the traces - something I thought is recommended. However, only Cyclone IV seems to insist on these. Useful to have them anyway - for future reference.

    What do the data and clock signals look like? Have a look at the clock's signal integrity as close to the memory device as possible. Any glitches? How long are the traces?

    Do you see this behaviour for other FPGA images?

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi,

    For future references in which traces we have to use series resistors ?

    I am attaching the pcb trace length for flash signals.

    In other FPGA means in cyclone 5 gt evaluation board i tested this procedure,same procedure holds good there ,this behavior not showing .in that board nstatus not toggling at power on.

    Regards

    DEEPAK
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    PCB trace lengths look fine.

    Series resistors - look at figure 8-2, page 8-11, of the "configuration and remote system upgrades in cyclone iv devices (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51008.pdf)" chapter of the handbook.

    Have you a captured clock and data going into the FPGA?

    What does the relative timing look like?

    What speed are you trying to configure at?

    Have you tried delaying boot by holding nCONFIG low for longer after power up?

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi,

    I tried delaying boot by holding nconfig low for longer after power up ,than also same issue.

    I attached the power sequencing and delay between the power supply ,please once check it.

    we are giving supply first to VCC (core supply),than VCC_aux,VCC_fpll,VCC_bat ,than VCC_pgm,VCC_pd ,VCCIO.

    Is it required to power up first VCC than (VCC_PGM,VCC_PD,VCCIO) than we power up (VCC_AUX,VCC_FPLL_VCC_BAT).

    Regards

    Deepak
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I presume that the power supply have tens to hundreds of microseconds rise time each, thus specifying nanosecond delays is meaningless respectively erroneous.

    Expected power-up sequence is clearly specified in the Quartus device handbook. Read it.