Is CPLD required for booting CYCLONE 5 FPGA from QSPI flash.

PCB trace lengths look fine.

Series resistors - look at figure 8-2, page 8-11, of the "configuration and remote system upgrades in cyclone iv devices (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51008.pdf)" chapter of the handbook.

Have you a captured clock and data going into the FPGA?

What does the relative timing look like?

What speed are you trying to configure at?

Have you tried delaying boot by holding nCONFIG low for longer after power up?

Cheers,

Alex