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Altera_Forum
Honored Contributor
8 years ago --- Quote Start --- During configuration nstatus is not going low --- Quote End --- Do you mean during FLASH programming nSTATUS is not going low? nSTATUS toggling when you reset/power cycle is not good, it suggests the FPGA is seeing an error. How quickly is it toggling and what are the other configuration signals (DCLK, nCONFIG, DATA0) doing relative to nSTATUS? If possible, I suggest you post some of your schematic. Cheers, Alex