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Altera_Forum's avatar
Altera_Forum
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8 years ago

Is CPLD required for booting CYCLONE 5 FPGA from QSPI flash.

in cyclone 5- fpga can’t able to fetch the program from spi flash FPGA - cyclone 5 (5cgtfd7d5f27i7n) SPI FLASH - epcq128si16n in our board only one spi flash (configuration flash) is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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Do you mean during FLASH programming nSTATUS is not going low?

nSTATUS toggling when you reset/power cycle is not good, it suggests the FPGA is seeing an error. How quickly is it toggling and what are the other configuration signals (DCLK, nCONFIG, DATA0) doing relative to nSTATUS?

If possible, I suggest you post some of your schematic.

Cheers,

Alex

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I attached the flash and power module schematic.

Nstatus is toggling that time duty cylce is 60(off time 40).

I attached the scope shot after programming flash when i power cycle the board.

Regards

Deepak