Is CPLD required for booting CYCLONE 5 FPGA from QSPI flash.

Your power up sequence looks OK. Refer to the 'Power-Up Sequence Recommendation for Cyclone V Devices' section, page 10-4, of the 'cyclone v device handbook (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf)'. Note the comments about monotonicity and meeting the T_ramp time.

Also consider the 'Power Pin Connections' section, page 12, of the 'arria v and cyclone v design guidelines (https://www.altera.com/en_us/pdfs/literature/an/an662.pdf)'.

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...ensure that the minimum current requirement for the power-on-reset (POR) supplies is available during device power up.

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Are your power supplies good enough for this? Note the maximum currents required in Table 10-1: "Maximum Power Supply Current Transient and Typical Duration", in the Device Handbook. If the supplies dip at all during power up the device may not start properly.

Are ALL you device's power pins connected? Do you have a schematic/symbol/footprint issue?

I'm suspecting this is power related.

Cheers,

Alex