Is CPLD required for booting CYCLONE 5 FPGA from QSPI flash.

I can't see anything wrong with the schematic. You don't have any series resistors in any of the traces - something I thought is recommended. However, only Cyclone IV seems to insist on these. Useful to have them anyway - for future reference.

What do the data and clock signals look like? Have a look at the clock's signal integrity as close to the memory device as possible. Any glitches? How long are the traces?

Do you see this behaviour for other FPGA images?

Cheers,

Alex