How to set timing constraint to uart

Question

uart is  used as interface of external device. And this device has it's owner clock. When doing timing constraint, should I set uart rxd and txd as false path? or setting timing constraint using virtual clock? or  just set max delay?

khaichein_y_intel · Answer

Hi,You may constrain the I/O signal max and min delay with reference to the virtual clock and any timing exceptions if applicable. You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf (Page 9 I/O Constraints)ThanksBest regards,KhaiY

xqshen · Answer

as there is no directly between FPGA clock and external device clock, how do you define the max or min limit?

khaichein_y_intel · Answer

Hi,Do you mean there is no direct relationship between the FPGA clock and external clock? Could you elaborate?ThanksBest regards,KhaiY

xqshen · Answer

Yes. They are two individual device using uart to communicate. 
FPGA ------uart---------external device(wifi module).

xqshen · Answer

1. FPGA has its own clock
2. Wifi module has its own clock

Forum Discussion

How to set timing constraint to uart

7 Replies

Recent Discussions

Quartus Programmer 21.1: JTAG Server Error Code 82 – Port 1309 Cannot Be Bound

Unable to Generate Valid PAM4 Eye Diagram and BER Measurements on Stratix 10 SI E-Tile Native PHY

Cannot program cyclone IV with USB blaster

Marking codes of CY10CL040YF484

Unable to scan JTAG chain, TCK only 2V