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Occasional Contributor

5 years ago

How to set timing constraint to uart

uart is used as interface of external device. And this device has it's owner clock. When doing timing constraint, should I set uart rxd and txd as false path? or setting timing constraint using virt...

KhaiChein_Y_Intel

Regular Contributor

5 years ago

Hi,

You may constrain the I/O signal max and min delay with reference to the virtual clock and any timing exceptions if applicable. You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf (Page 9 I/O Constraints)

Thanks

Best regards,

KhaiY

XQSHEN
Occasional Contributor
5 years ago
as there is no directly between FPGA clock and external device clock, how do you define the max or min limit?

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How to set timing constraint to uart

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