How to Interface 10M04SCU169 with Host processor

Put the FPGA design together and let Quartus help you.

How many control signals is up to you and the constraints of the processor - i.e. what control signals it has to offer. You mention RD and WR. Fine. If this interface is to be shared with other peripherals then a dedicate chip select (CS) for the FPGA will be required too. If it's not shared then you can do without CS.

Once you have an FPGA design Quartus will/can select I/O for you. Depending on any other requirements you have you're probably best guiding it through the pin planner. Keeping the Micro interface to one bank of the FPGA may be advantageous, for example. See this "my first fpga tutorial (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/tt/tt_my_first_fpga.pdf)" for help with the Pin Planner - although there is plenty of other online help out there too.

Cheers,

Alex

Thank you,

But still, i am not clear about the number of minimum I/O line

Could you please let me know minimum I/O pins required to interface FPGA and Microcontroller

Can I connect any I/O pin to MCU for address, data and control lines

OR is there any specific pin for the MCU and FPGA interface?

I am not able to run or check pin planner because of not aware and time limit

if any sample document with of 10M04SCU169 pls. share link

at least share minimum control lines required for interface

What micro are you using? How many I/O lines does it have for memory mapped peripherals?

Yes - you will be able to connect the micro to any GPIO on the FPGA. There are no specific pins on the FPGA that you must use.

Cheers,

Alex

--- Quote Start ---

What micro are you using? How many I/O lines does it have for memory mapped peripherals?

Yes - you will be able to connect the micro to any GPIO on the FPGA. There are no specific pins on the FPGA that you must use.

Cheers,

Alex

--- Quote End ---

Within limits, however. If the micro has 3.3V I/O, and the FPGA has multiple I/O banks, you must the I/Os populated in a compatible voltage bank.

You may be using 1.8V or 2.5V I/O for some other interfaces, so those banks may not be compatible with a 3.3V I/O CPU interface requirement.

So some planning will be necessary to choose where you connect the I/Os, but as indicated you will have a lot of flexibility of choice within an I/O bank.

--- Quote Start ---

Within limits, however. If the micro has 3.3V I/O, and the FPGA has multiple I/O banks, you must the I/Os populated in a compatible voltage bank.

You may be using 1.8V or 2.5V I/O for some other interfaces, so those banks may not be compatible with a 3.3V I/O CPU interface requirement.

So some planning will be necessary to choose where you connect the I/Os, but as indicated you will have a lot of flexibility of choice within an I/O bank.

--- Quote End ---

Thanks a Lot

Micro is RX631 169 BGA package from Renesas, Working on 3.3V VDD

FPGA is also working on single supply 3.3V voltage

RX631 is having 2 WAIT signal, 6 Chip Select, Write and Read signals and 24 address and 16 data lines

We have LAN9252 ESC interfaced to RX631 Micro by 4 address line and 15 Data Line

So, please guide us about How to interface FPGA to Micro and LAN9252 to FPGA using address and data line

i have attached pin mapping connection diagram

pls. revert back with suggestion and comments

--- Quote Start ---

What micro are you using? How many I/O lines does it have for memory mapped peripherals?

Yes - you will be able to connect the micro to any GPIO on the FPGA. There are no specific pins on the FPGA that you must use.

Cheers,

Alex

--- Quote End ---

Micro is RX631 from Renesas make and 169 BGA package

Could you please explain with example -that how to connect FPGA 10M01SCU to RX631 Micro

pls share the other links also

Do we required Wait signal for the interface?

How many address and data requried ?

--- Quote Start ---

Micro is RX631 from Renesas make and 169 BGA package

Could you please explain with example -that how to connect FPGA 10M01SCU to RX631 Micro

pls share the other links also

Do we required Wait signal for the interface?

How many address and data requried ?

--- Quote End ---

From your description the uP has all 3.3V I/O, and so does your FPGA, so you can connect pins more or less as you desire. If your PCB is constrained you may want to choose an FPGA pinout that makes routing signals to your uP as simple as possible.

As to how many address/data/select/wait lines to use, well it depends upon your application. You know that; I don't. Probably I would connect all of them, unless your FPGA is going to be I/O constrained for other signals. It is always easier to ignore or not use signals, but a lot more problematic if you need a signal that is not connected.

--- Quote Start ---

From your description the uP has all 3.3V I/O, and so does your FPGA, so you can connect pins more or less as you desire. If your PCB is constrained you may want to choose an FPGA pinout that makes routing signals to your uP as simple as possible.

As to how many address/data/select/wait lines to use, well it depends upon your application. You know that; I don't. Probably I would connect all of them, unless your FPGA is going to be I/O constrained for other signals. It is always easier to ignore or not use signals, but a lot more problematic if you need a signal that is not connected.

--- Quote End ---

Thank a lot

For FPGA we have 3.3V for All I/Os

Application means memory size required for our use?

Or Could you please share how to decide address and the data line for particular memory size?

For example - to access 512MB How many addresses and data lines required?

For 1GB How much? and for 4 GB How much?

--- Quote Start ---

Thank a lot

For FPGA we have 3.3V for All I/Os

Application means memory size required for our use?

Or Could you please share how to decide address and the data line for particular memory size?

For example - to access 512MB How many addresses and data lines required?

For 1GB How much? and for 4 GB How much?

--- Quote End ---

'Application' means what are you trying to do with the FPGA in your system. You have never said, so I can only make very general usage comments.

As to number of address and data bits required to support a particular memory size requirement that is fairly straightforward. Number of address bits is ceil(log2(memsize)). Example, for 1Mb memory you need 20 bits.

Data bit width depends on your uP, the memory, and required access bandwidth. So it depends on your application.

From the questions you ask you seem to be very new to hardware and FPGA design, so I might suggest finding someone local to you that has more experience and can mentor you.

The address line usage doesn't seem to be well considered. You want mutual exclusive address ranges for network controller and FPGA. Can be either achieved by using different chip selects or a high address bit fed into an address decoder.

The FPGA processor interface will preferably connect address bits starting at A0 (presumed this is lowest word address line) to get consecutive register addresses.

If high bus throughput is an objective, you should check the option to clock the bus interface with BCLK.