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The address line usage doesn't seem to be well considered. You want mutual exclusive address ranges for network controller and FPGA. Can be either achieved by using different chip selects or a high address bit fed into an address decoder.
The FPGA processor interface will preferably connect address bits starting at A0 (presumed this is lowest word address line) to get consecutive register addresses.
If high bus throughput is an objective, you should check the option to clock the bus interface with BCLK.
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Thank you
I will use BCLK for bus clock
In our application, as i mentioned three major components
FPGA MAX 10 series 10M04SCU169 , LAN9252 ESC and RX631 CPU
All i want to interface to FPGA, Now which address and how many lines to use I don't know?
please find attached block diagram - signal connection
and revert back your review comments
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