Forum Discussion
Altera_Forum
Honored Contributor
8 years ago --- Quote Start --- You should know how large the intended FPGA register map is, if you possibly want additional dual port RAM. The decision rules the number of required address lines. The other parameter is data throughput. I already suggested a separate CS line for FPGA interface. A serial (SPI) interface would be a low pin count alternative for moderate data throughput. --- Quote End --- yes, we want to use DPRAM from the FPGA if the signal diagram is incorrect, pls advise what and where to correct in diagram.