How to Interface 10M04SCU169 with Host processor

The address line usage doesn't seem to be well considered. You want mutual exclusive address ranges for network controller and FPGA. Can be either achieved by using different chip selects or a high address bit fed into an address decoder.

The FPGA processor interface will preferably connect address bits starting at A0 (presumed this is lowest word address line) to get consecutive register addresses.

If high bus throughput is an objective, you should check the option to clock the bus interface with BCLK.