Forum Discussion
Honored ContributorHow to get 45Mhz clock out?
Hi dears:
I am using ArriaGX devices, and the board's clock is 100Mhz which is input to the FPGA. And the system need a 45MHz clock, could you have any method to generate this clock through FPGA's PLL? Otherwise i have to use aonther 45Mhz oscillator. Thanks! Jerry27 Replies
Altera_ForumThere is really nothing new in my rate generator. It is the same issue as any other clock enable.
There are many designs we talk about that use clken and possibly 100s of posts about it. The only difference is that I am talking about various schemes of enable generation itself. The small details can only make sense in the context of a given application.- Altera_Forum--- Quote Start --- and my data is at 45MHz nominal rate --- Quote End --- Where is the 45MHz nominal rate defined? I only see a 'virtual' 45MHz rate in a 100 MHz system where everything is running at a 100 MHz (avoiding clock domain crossing) and where you sub- or down-sample the incoming stream to this 'virtual' 45 MHz (using the described add/modulo technique) and then, after possibly performing mixing or other operations with other signals, upsample it back to 100 MHz. But if the input data is coming from e.g. a 45 MHz ADC there will be clock domain crossing involved, somehow?
- Altera_Forum
it is the rate of 100MHz clock slowed down by invalid slots resulting in an effective rate of 45MHz from processing perspective.
If I run my upsampler on 100MHz, and my data is at 45MHz nominal rate then I will run data section on same 100MHz clock but conditioned on clken i.e. I will send request (= clken) backwards to read data and push it through upsampler. The upsampler is based on filters. Passing domains has multiple meanings(depends on perspective): 1) ordinary two clock domain passing of data at its rate (no change of effective rate) 2) cross from one sampling rate to another by creating new samples or removing samples so that the signal carries same info (DSP perspective) This same as if you use an ADC of say 112MHz to sample a signal that was originally on 76MHz. - Altera_Forum--- Quote Start --- No, we are talking about one clock domain. The 100Mhz will clock all the registers conditioned on clken to slow it down to 45MHz rate. There is no need for fifos since we are not talking about two clocks. --- Quote End --- Still puzzled where the 45 MHz rate comes from? As you are (e.g.) upsampling data from 45 MHz to 100 MHz, there must be a 45MHz clock (internal or external) involved as well?
- Altera_Forum
No, we are talking about one clock domain. The 100Mhz will clock all the registers conditioned on clken to slow it down to 45MHz rate.
There is no need for fifos since we are not talking about two clocks. - Altera_Forum
(I think we are going a bit off-topic here ... continuing regardless)
I assume there is some clock domain crossing involved going from a low input rate to the high output rate? Then I see a dcfifo in the path which does this rate adapting automatically? Or do you think this produces more jitter? - Altera_Forum
I have used this method for various projects esp. when upsampling data by variable fractions towards the DAC rate. symbol rate may vary in systems and need be uplifted to DAC rate. on the same fixed system clock I generate an enable "backpressure" from upsampler module running at system clock to request data at its lower rates.
- Altera_Forum--- Quote Start --- use modulo adder: accumulator that adds up 45 modulo 100, produce an en pulse at overflow. I posted this recently in code:evil:. --- Quote End --- --- Quote Start --- or add 9 modulo 20 (same ratio) alternatively, if the application tolerates use 9 clocks with enable ON then 11 clocks with enable off: http://www.alteraforum.com/forum/showthread.php?t=29224 --- Quote End --- Where would or do you use this method ?
- Altera_Forum
or add 9 modulo 20 (same ratio)
alternatively, if the application tolerates use 9 clocks with enable ON then 11 clocks with enable off. or alternate enable ON/OFF for 18 locks then OFF for two clocks. The modulo adder is much neater reusable way... http://www.alteraforum.com/forum/showthread.php?t=29224 - Altera_Forum
use modulo adder: accumulator that adds up 45 modulo 100, produce an en pulse at overflow. I posted this recently in code:evil:.
