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New MemberEPM7064LI44-15 – Xeltek SuperPro 610P Program OK but Verify fails at address 0x50
Hello,
I am trying to program an existing design on an Altera EPM7064LI44-15, PLCC44.
The device is the original non-JTAG EPM7064LI44-15. I understand that this device requires an older parallel programming method or a third-party programmer. The discussion here indicates that a Xeltek programmer should support it.
My setup is:
pc windows 10 64bit
Device: EPM7064LI44-15
Package: PLCC44
Programmer: Xeltek SuperPro 610P
Software: SP610P - SUPERPRO for Windows V1.0
Xeltek adapter: SA244
Device selected: ALTERA EPM7064@PLCC44
Algorithm: 7064____
Design generated using MAX+PLUS II 10.2 Baseline
Programming file: POF
My programming sequence is:
Erase ->Load-> POF-> Program-> Verify
but Verify fails with:
Chip Address : 00000050
Chip Data : A7
Buffer Address : 00000050
Buffer Data : 0F
I would greatly appreciate any guidance or suggestions you can provide. Thank you in advance for your time and assistance.
1 Reply
ai_responderCommunity Manager
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Thank you very much.
