How to find out a Tco from TimeQuest

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That would be useful indeed for delay measurements. I used signaltap at some point just to measure delays.

For mobile Tx/Rx systems all delay figures are important and have to be worked out by various engineers part of which is FPGA.

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Yes, kaz! So I think it would be great if such a total delay command would be inserted in TQ.

That would be useful indeed for delay measurements. I used signaltap at some point just to measure delays.

For mobile Tx/Rx systems all delay figures are important and have to be worked out by various engineers part of which is FPGA.

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data transition at first reg is sampled into reg2 then reg3 ...etc. This is latency issue and you the designer will know that. The tool does not change latency as it is vital for functionality.

Any routing/logic delays between registers is absorbed into the sampling periods.(normally 1 period unless multicycle > 1)

so what you want is [pin-to reg1 delay + number of regs in chain x clock period + last reg to pin delay]. =~ number of reg x clock period

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Yes, kaz, I absolutely agree with you! I just thought that there is a command to find out that value automatically without manual calculation.

Thank you very much!

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Hi kaz!

Yes, exactly, as about tCO parameter it is what you wrote. I was interested if there is such parameter that sum tCO and integrated clock cycles on other register (a path from input pin to output pin with intermediate registers inside the path).

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data transition at first reg is sampled into reg2 then reg3 ...etc. This is latency issue and you the designer will know that. The tool does not change latency as it is vital for functionality.

Any routing/logic delays between registers is absorbed into the sampling periods.(normally 1 period unless multicycle > 1)

so what you want is [pin-to reg1 delay + number of regs in chain x clock period + last reg to pin delay]. =~ number of reg x clock period

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As also stated in that doc you linked to:

tCO is meant to be time from clock edge at clock pin input (that clocks the output register) to data transition at output pin of that register(if its input changes). You don't need to sum up clock cycles on any other registers (that is latency)

tCO is not used for combinatorial paths. It = clock delay from pin to register + register micro tCO + register to pin delay

So I do feel it is what you are after.

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Hi kaz!

Yes, exactly, as about tCO parameter it is what you wrote. I was interested if there is such parameter that sum tCO and integrated clock cycles on other register (a path from input pin to output pin with intermediate registers inside the path).

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Well, it is not exactly what I needed because my task was to find out total amount of delay from input pin to output pin in system like in example I added in the beginning of the thread (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/wp/wp_stxtco.pdf). But I think it only works for a combinational path, if there are more than one register in the path we need to manually sum clock cycles to Tco of output register.

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As also stated in that doc you linked to:

tCO is meant to be time from clock edge at clock pin input (that clocks the output register) to data transition at output pin of that register(if its input changes). You don't need to sum up clock cycles on any other registers (that is latency)

tCO is not used for combinatorial paths. It = clock delay from pin to register + register micro tCO + register to pin delay

So I do feel it is what you are after.

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I think you want the datasheet report.

http://quartushelp.altera.com/15.0/mergedprojects/analyze/sta/sta_com_report_datasheet.htm

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Hi, rbugalho! I tried your suggestion. I started "Report Datasheet" task and looked into "Clock to Output Times" part of output report. As I understand, "Clock to Output Time" means total delay from input clock pin transition to resulted output pin transition, in my case through the last register in the path (the register which feeds output pin directly). I compared that delay to a sum of clock and data delay from report_timing and they are equal!

Well, it is not exactly what I needed because my task was to find out total amount of delay from input pin to output pin in system like in example I added in the beginning of the thread (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/wp/wp_stxtco.pdf). But I think it only works for a combinational path, if there are more than one register in the path we need to manually sum clock cycles to Tco of output register.

It looks like TQ considers that report as something legacy information. I suppose it is not a very useful task because I can't locate full path directly from report generated by that task. For me more useful trick is to use Report All I/O Timings Macros and choosing pins needed launch Report Timing commands.

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I think you want the datasheet report.

http://quartushelp.altera.com/15.0/mergedprojects/analyze/sta/sta_com_report_datasheet.htm

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Thank you very much, rbugalho. I will try your suggestion and write if it helps!

I think you want the datasheet report.

http://quartushelp.altera.com/15.0/mergedprojects/analyze/sta/sta_com_report_datasheet.htm

Hi, sstrell!

Maybe some other thoughts, do you agree with my opinion?